Substrate for an electric component and method for the production thereof

ABSTRACT

For a component mounted with the flip-chip technique, in particular surface wave elements, it is proposed to use a low-shrinkage ceramic substrate over which (as needed) multi-layer metallizations are produced by metal deposition. The bumps can also be produced by self-aligning metal deposition.

[0001] With the help of flip-chip technology, it is possible to affixand bond surface wave components in a simple manner to a carrier (forexample, a circuit board), to thereby arrange the component so it ismechanically protected, and to further reduce in size the entireassembly. In addition, the piezoelectric substrate on which the surfacewave element is realized in the metallized form is provided withsolderable contacts on the surface. Corresponding cooperating contactsthat provide solder pads are on a base plate, for example a ceramicmulti-layer plate made from HTCC-ceramic. These solder pads are arrangedby feedthroughs in the base plate or connected to it via metallicconductor paths, such that the electrical connection can ensue to theback side of the base plate. With the metallization facing down, thesurface wave substrate is now mounted on the base plate and theconnection between the solder pads and the solderable contacts on thechip is made with the aid of solder hunches—bumps.

[0002] The component structures on the chip thereby remain spaced fromthe base plate and are mechanically protected in the intervening spaceformed between chip and base plate. It is also possible to protect thecomponent structures before the mounting of the chips on the base platewith the aid of a covering that, for example, can be generated in anintegrated procedure from two-layer materials capable of beingphotostructured. The component structures are thereby better protectedagainst environmental influences. To further seal the component, it ispossible to cover the chip, for example, with a film or a layer thatterminates tightly with the base plate. In addition, a radiofrequencyshield of the surface wave component is possible with the aid of a metallayer or metal sub-layer.

[0003] With increasing miniaturization of surface wave componentsmounted with the flip-chip technique, the demand for base plates and theassembly technologies used is rising. For example, a larger number ofbump connections are needed per unit of area that are often no longerrealizable with reasonably priced methods. The application of bumps andconductor paths on the base plate ensues in a cost-effective manner bymeans of screen printing. Bump separations of up to a minimum of 250 μmand bump diameters or, respectively, conductor paths of a minimum of 80μm can be thereby produced. Conductor path widths of a minimum of 80 μmare produced. If still smaller structures should be produced, an exactalignment of the structures on the base plate is no longer possible.This problem is aggravated in that the feedthroughs of the base plateare already produced in the phase of the ceramic green film. The greenfilm is then transferred to the final hard ceramic by sintering.Admittedly, a shrinkage of surface area that entails an error of morethan 0.2% is associated with commonly used HTCC-ceramic. This makes aprecise alignment of the bumps and conductor paths to be printedimpossible.

[0004] The object of the present invention is therefore to specify asubstrate or, respectively, a base plate for components to whichflip-chip technology is applied, in particular surface wave components,in which a precise alignment of the component is possible in furtherprogressive miniaturizations. A further object concerns the productionof such a substrate.

[0005] This object is inventively achieved by a substrate with thefeatures of claim 1. Advantageous embodiments of the invention as wellas the method of production of the substrate arishe [sic] from furtherclaims.

[0006] The invention proposes to use a ceramic having low warping assubstrate for flip-chip-mounted components, and to produce the requiredconductor paths and under-bump metallization (solder pads) as necessaryon the substrate in the form of a multilayer metallization with the aidof a photostructuring in an additive or subtractive method, and to applybumps to them.

[0007] It is possible with such a substrate to clearly under-run thehitherto lower limit for bump separations of 250 μm and of bump andconductor path diameters of 80 μm, such that a further miniaturizationof components is possible in a simple manner. For example, componentswith external dimensions of 5×5 mm² or better can be produced with theinvention. Since the production of bumps can ensue in aquasi-self-aligning manner on an inventively photolithographicallyproduced underbump metallization, bumps can be produced for the laterflip-chip mountings with a distance of less than 100 μm. Nevertheless,it is possible with the invention to implement all processing steps withhigher alignment precision, such that the component is produced withgreater reliability and with little waste.

[0008] The inventively used ceramic having low warping shows a shrinkageduring sintering with an error of less than 0.1% which allows, withinthe range of the allowable tolerance limits, a precise alignment of themetallization on the substrate relative to the feedthroughs placedbefore the sintering. For example, an especially low-shrinkage ceramicis a selected non-shrinkage LTCC-ceramic (Low Temperature CofiredCeramic).

[0009] A feedthrough conventionally produced by stamping the green film,for example, usually exhibits a diameter of 150 μm. In exacting methods,feedthroughs with diameters of 100 μm or even 80 μm may also beproduced. However, since an inventive substrate can comprise bumpdiameters of less than 75 μm, it is advantageous to not produce thesolder pads directly on the substrate for the definition of the bumps,but rather to realize these in a multilayer assembly which comprises atleast one isolation layer over the substrate and at least oneelectrically conductive layer over the isolated layer. Any wiringpatterns and solder geometries may be realized in a simple manner insuch multi-layer metallizations. Large-area connection surfaces forcontacting the feedthroughs can thus be covered with isolation layers,over which small-surface solder pads with slight distance can then beproduced as under-bump metallization. A compensation that enablessmaller bump dimensions and distances is thus allowed for theimprecisions caused in the ceramic substrate.

[0010] The isolation layers for the multi-layer metallizations canpreferably be photostructured and, especially advantageously,implemented as light-sensitive photoresists. Appropriate base polymersfor these isolation layers that can be photostructured can be polyimide,polybenzoxazol (PBO), or benzocylcobutene (BCB), known for hightemperature durability. These polymers can be implemented either asnegatively operating photoresists which cross-link in irradiatedregions, are thereby insoluble, and which thereby increases theirthermal and chemical resistances, or as positive resists whosesolubility can be increased by irradiation.

[0011] In the additive method, the metallizations are first defined bymeans of a photoresist or isolation layers that can be photostructured.In addition, a base metallization can first be applied, for example bysputtering or vacuum deposition. This is subsequently covered with astructured resist layer or photoresist layer in which the regions to bemetallized are bared. The metallization in the bared regions is isolatedfrom the solution for the thickening-up of the base metallizations. Thisis suited as well to zero-current as well as galvanic methods that canbe used in combination in an advantageous manner. A multi-layermetallization comprises, for example, an adhesive layer or seed layer, arapidly grown conducting layer, and on top of that normally apassivation layer made from a metal that is oxidation-resistant or whichis shows an appropriate passivation by means of a provided thin oxidelayer. A range of methods are known for such metallization, however theyare not the subject matter of the invention.

[0012] In possible methods that are likewise subtractive, themetallizations are first applied by vapor deposition or sputtering overthe entire surface in the desired layer thickness, and only afterwardsstructured, for example by means of etching using a structured resistlayer as etching template.

[0013] The exact geometric definition of the metallization in the layercapable of being photostructured is possible by means of plastic [sic]exposure that can be implemented with a correspondingly alignedphotomask. However, it is also possible to implement the exposure of thelayer capable of being photostructured by means of a scanned laserexposure that cane be implemented in a self-aligning manner with the aidof orientation markings on the substrate.

[0014] It is possible in an embodiment of the invention to use one ormore feedthroughs as alignment markers for the self-aligning scannedlaser exposure. This guarantees an exact relative positioning of themetallic structures on the substrate relative to the feedthroughsalready previously existing.

[0015] In the following, the invention is more closely explained usingan exemplary embodiment and the seven figures belonging thereto.

[0016] Using schematic cross-sections, the figures show various methodsteps in the production of an inventive substrate equipped, for example,with a surface wave component.

[0017] The figures serve only for the better understanding of theinvention and show no scale images of the component.

[0018] For example, a ceramic green film made from an LTCC-material isprovided by stamping with feedthroughs D necessary for externalconnections. The film is sintered, whereby it exhibits an exactlydefined lateral shrinkage of less than 0.1%. FIG. 1 shows the substrateprovided with the feedthroughs D in this state.

[0019] A first layer P1 capable of being photostructured is now appliedto the entire surface of the substrate S and plastically [sic] exposedin order to define a first metallization layer. The layer capable ofbeing photostructured, that also serves later as the isolation layer, isremoved after the procedure from the locations that are provided for thefirst metallization M1. FIG. 2 shows the arrangement of the alreadyphotostructured layer P1.

[0020] A thin metal layer M1 is deposited here for the metallization bymeans of a zero-current metal deposition and preferably galvanicreinforcement in the regions that are not covered by the first layer P1capable of being photostructured, namely in the area of the requiredconductor paths and soldering pads. The thickness of the firstmetallization layer M1 is determined by appropriate depositionrequirements, and its current conductivity is determined together withthe metal selection.

[0021] A second layer P2 capable of being photostructured is now appliedover the entire surface of the assembly. The surfaces in the firstmetallization layer M1 are bared by photostructuring, showing thesoldering pads for acceptance of the bumps, thus the under-bumpmetallization. FIG. 4 shows the arrangement of the first metallizationlayer M1 after baring the regions prepared as solder pads LP.

[0022] The bumps B are now produced over the solder pads LB, preferablyby galvanic deposition of a metal appropriately used for solder or analloy, for example a lead/tin alloy. Since the second layer P2 capableof being photostructured serves as a template in the galvanicdeposition, the method for the production of the bumps is self-aligning.Stencil printing for generating the bumps is also appropriate for bumpdimensions between 50 and 100 μm. FIG. 5 shows the arrangement after theproduction of the bumps B. In addition, the SMD metallizations T, withthe aid of which the substrate S can later be soldered to a circuitboard, can still be produced at this stage of the method on the backside of the substrate S.

[0023] An electrical component, for example a surface wave component, isnow soldered using the flip-chip technique onto the prepared substratefinished thusly. In addition, the piezoelectric chip C, which compriseson its top side the component structures in the form and electricallyconductive structures L, is placed upon the bumps B with the componentstructures L facing the substrate S. In addition, the chip C comprisessolderable metallizations on the (downward facing) surface that form thecontact metallizations for the component structures L. The soldering iseffected by melting open the bumps B. The arrangement is shown in FIG. 6in this stage with the surface wave component realized on the chip C. Inaddition, FIG. 6 shows a protective covering designated by the applicantas PROTEC, which is placed over the component structures as a cap. Thecovering is preferably comprised of one of the borders R enclosing thecomponent structures L, which simultaneously forms support andseparation component for the covering layer A. In this manner, thecomponent structures L are securely housed in an opening H betweencovering A and chip C.

[0024] Although a sufficient protection from environmental influences isgiven for the component structures by the PROTEC covering, the chip Ccan be covered even further by a protective layer SS. This lies on theback side of the chip C and terminates tightly with the upper substratelayer P2. The protective layer SS can be a multi-layer film laid overthe component, as needed. However, it is also possible to produce theprotective layer on the component by material deposition, and ifnecessary to structure it in the border areas. This can be supportedwhen the undercut U is filled with a flow-capable filling compoundbetween the border area of the chip C and the surface of the substrateS, on which the protective layer C may be then applied in a simplemanner, for example by vacuum deposition or sputtering of a metal.

[0025]FIG. 7 shows the component with the completed protective coveringSS. Since all previous method steps were preferably implemented in thepanel, in that a plurality of chips are mounted in a process step on alarge-area substrate, the separation of the individual components cannow ensue. FIG. 7 shows such an individual component which iseffectively protected against environmental influences, in particularmechanical effects, humidity, dust, or chemicals. The total dimensionsof the component are only slightly larger than the surface of the chip,[and] are therefore exceedingly space-saving and are designated by theapplicant as CSSP (Chip Size SAW Package).

[0026] Although described only by a single exemplary embodiment, theinvention is not limited to this. In particular, it is also possible toselect a multi-layer composition for the substrate S, in that aplurality of the shown green films can be combined as needed under theintermediate arrangement of conductor path structures into a thickermulti-layer substrate. The composition of the metallization on thesurface of the substrate also does not have to conform to the shownform. It is also possible to produce further metallization layers of anystructure and thickness. This latter can serve for the better alignmentof the solder pads upon which the bumps are finally produced in aself-aligning manner. The surface wave chip can comprise one or morePROTEC coverings, can however also be mounted on the substrate withoutthis covering. Some some [sic] component can also be processed, mounted,and protected in this manner, for example an IC or also a passivecomponent. The protective layer SS can be one-layer or multi-layered,whereby a metal layer can comprise one or more of these layers.Furthermore, it is possible to also cover the entire component above theprotective layer SS with a cast resin or to extrusion-coat the entirecomponent above the protective layer SS with a plastic compound, whichserves to further protect the component.

1. Substrate with components (C)—chips—mounted thereon with flip-chiptechnique by means of bumps (B), characterized in: that the substrate(S) comprises at least one layer of a non-warping ceramic; thatfeedthroughs (D) are provided through the (minimum one) layer; thatunder-bump metallizations facing the chip that are connected to thefeedthroughs via conductor paths are provided on the substrate, and;that the bumps (B) deposited galvanically or without current are formedfrom a multi-layer metallization (M1).
 2. Substrate according to claim1, in that the separation of the bumps (B) are less than 75 μm. 3.Substrate according to claim one or 2, in that the substrate comprisesan LTCC ceramic.
 4. Substrate according to any of the claims 1 through3, in that the substrate (S) comprises a ceramic that is low-warpingduring sintering, whose shrinkage after the sintering exhibits an errorof less than 0.1%.
 5. Method for the production of a substrate forcomponents—chips—(C) mountable by flip-chip technique by means of bumps(B): in that openings for feedthroughs are produced in a low-warpingceramic green film; in that a plurality of green films as needed withconductor paths between them are combined into a multi-layer assembly(S); in that the (as needed) multi-layer assembly is sintered; in that,on the surface of the assembly, soldering pads (LP) connected to theconductor paths by the feedthroughs are defined by means of aphotostructuring, and are reinforced by means of a galvanic and/orcurrent-less metal deposition.
 6. Method according to claim 5, in thatan LTCC ceramic film is used as green film, in which the sinteringshrinkage incurs an error of less than 0.1%.
 7. Method according to anyof the claims 5 or 6, in that a photoresist layer (P1) is applied overthe entire surface for the photostructuring, plastically exposed, andsubsequently processed.
 8. Method according to claim 7, in that ascanned laser exposure is implemented for the plastic exposure of thephotoresist layer (p1).
 9. Method according to claim 8, in that aself-aligning scanned laser exposure is implemented, whereby thefeedthroughs (D) are used as alignment markers.
 10. Method according toany of the claims 5 through 9, in that conductor paths and solder pads(LP) are realized in a multi-layer assembly (M1), for which at least oneisolated layer (P1, P2) and one conductive layer (M1) are produced one atop the other.
 11. Method according to claim 10, in that the isolatedlayers (P1, P2) capable of being photostructured which are chosen frompolyimide, polybenoxazol, or benzocyclobutene are produced for themulti-layer assembly.
 12. Method according to any of the claims 5through 11, in that an electrical component, in particular a surfacewave component (C) with surface wave structures (L) facing the substrateover its solderable metallizations, is placed and soldered upon bumps(B) produced over the solder pads (LP).